The present invention disclosed herein relates to an analog digital converting device, and more particularly, to a successive approximation analog digital converter.
Recently, as the use of a mixed-mode system increases, the necessity of an analog digital converter (hereinafter referred to as ADC) is in a progressively increasing trend. Particularly, in systems such as Digital Video Disk Players (DVDPs) and Direct Broadcasting for Satellite Receivers (DBSRs), research is being actively conducted for one chip based on a Complementary Metal-Oxide Semiconductor (CMOS) process for the effective-cost. For this, an ADC design technology for directly processing a Radio Frequency (RF) signal is becoming an increasingly important issue.
Up to date, various types of ADCs have been proposed. Flash ADCs, pipeline ADCs and successive approximation ADCs are used in appropriate application fields in accordance with their characteristics. Generally, the flash ADCs have fast operation characteristic, but have a high power consumption rate. The successive approximation ADCs have a low power consumption rate and a simple circuit configuration, but have slow operation characteristic. Comparing with the flash ADCs and the successive approximation ADCs, the pipeline ADCs have the operation characteristic of an intermediate speed and an intermediate power consumption rate. Recently, research is being conducted on hybrid ADCs for supplementing the advantages and disadvantages of the above-described ADCs.